There are certain scenarios which prevent the execution of next instruction is called Hazard.
Hazards reduce the performance of pipeline. THere are three types of Hazards.
1. Structural Hazards: These are mainly because of resource conflict. When more than one instruction wants to access the same resource then this hazard will occur.
e. g. A processor which has shared data and instruction memory. When instruction contains data memory reference ( like load instruction ), it will cause conflict with instruction in its Fetch stage as both instructions are trying access shared memory.
Reason: To reduce the cost, if functional units are doubled to resolve structural hazard it may be too costly.
2. Data Hazards: When instruction depends on the result of previous instruction. In this case instruction attempts to use data before it is ready.
Solutions:
a. Forwarding technique / Bypassing / Short-Circuit: Ex | Mem, and Mem | WB registers are fed back to ALU input. If forwarding hardware detect that previous instruction result is available as input to ALU, the control unit selects the forwarded result instead of reading it from the register file.
b. Stall / Interlock: Always it's not possible to solve data hazards with forwarding in those cases need to stall pipeline until right data is available. Pipeline interlock hardware preserves correct execution pattern, it stalls pipeline until the hazard is cleared.
e.g. Here all the instructions after ADD use the result of ADD instruction. ADD instruction writes the value to R1 in WB stage whereas SUB instruction read the value during ID stage.
ADD R1, R2, R3
SUB R4, R1, R5
AND R6, R1, R7
OR R8, R1, R9
3. Branch / Control Hazard:
Hazards reduce the performance of pipeline. THere are three types of Hazards.
1. Structural Hazards: These are mainly because of resource conflict. When more than one instruction wants to access the same resource then this hazard will occur.
e. g. A processor which has shared data and instruction memory. When instruction contains data memory reference ( like load instruction ), it will cause conflict with instruction in its Fetch stage as both instructions are trying access shared memory.
Reason: To reduce the cost, if functional units are doubled to resolve structural hazard it may be too costly.
2. Data Hazards: When instruction depends on the result of previous instruction. In this case instruction attempts to use data before it is ready.
Solutions:
a. Forwarding technique / Bypassing / Short-Circuit: Ex | Mem, and Mem | WB registers are fed back to ALU input. If forwarding hardware detect that previous instruction result is available as input to ALU, the control unit selects the forwarded result instead of reading it from the register file.
b. Stall / Interlock: Always it's not possible to solve data hazards with forwarding in those cases need to stall pipeline until right data is available. Pipeline interlock hardware preserves correct execution pattern, it stalls pipeline until the hazard is cleared.
e.g. Here all the instructions after ADD use the result of ADD instruction. ADD instruction writes the value to R1 in WB stage whereas SUB instruction read the value during ID stage.
ADD R1, R2, R3
SUB R4, R1, R5
AND R6, R1, R7
OR R8, R1, R9
3. Branch / Control Hazard:
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